Blocking assignment for clock divider - Verification Academy
: Simulating 2 seconds of real time at 50 MHz will require 100 million clock cycles – this is fine in simulation but may take minutes to hours if you simulate full seconds. For quick tests, reduce the MAX_COUNT to something small like 10, then verify that the output toggles every 5 cycles. clock divider verilog 50 mhz 1hz
// Initialize rst_n = 0; #100;
endmodule