Verigy 93k Tester Manual =link= 📥 👑
Defines voltage thresholds (VIH, VIL, VOH, VOL) and power supply settings.
The Verigy 93k (now under the Advantest brand) was designed to address the increasing complexity of System-on-Chip (SoC) devices. Unlike older testers, the 93k utilizes a "tester-on-a-pin" architecture. This means every pin is independent, allowing for massive parallelism and flexibility.
Pin("DATA0", "IO", 1); // Channel 1 SetTiming("Timing1", 1000ns); SetEdge("R0", 200ns); SetEdge("F0", 600ns); ApplyPattern("func_pattern.bin"); verigy 93k tester manual
This is the domain of the test floor technician. The for maintenance details the Preventive Maintenance (PM) schedule. It instructs users on how to replace air filters, calibrate the system clock, and perform "Performance Verification" (PV). The PV manual is a subset that walks through the calibration routines required to ensure the tester meets ISO standards.
The 93k is famous for its wide range of pin cards (e.g., the HSD series for digital, the PS series for power). The manual for each specific card type is critical. These manuals contain the electrical specifications—voltage ranges, current limits, timing accuracy, and edge placement. Defines voltage thresholds (VIH, VIL, VOH, VOL) and
This is where the DUT connects to the tester. The manual provides specific torque and alignment requirements for the pogo-pin blocks. The Workstation
| Manual Title (Typical) | Content Focus | |------------------------|----------------| | | Overall system architecture, backplane, power supplies, cooling, site modules, security interlocks. | | SmarTest User Guide | GUI navigation, testflow creation, job submission, debug tools, datalogging. | | Digital Subsystem Manual | Pin electronics (P, P8, P16, P32, PX), timing generators, sequence control, pattern memory. | | Analog Subsystem Manual | AC/DC measurement units (AVI, DPS, MUs), floating sources, relay switching. | | RF Subsystem Manual | RF ports, up/down converters, calibrations for 93K RF options. | | DC Calibration Guide | Procedures for open/short, leakage, gain/offset cal on DPS, PMU, PVI. | | Tester Installation & Site Prep | Power, cooling, grounding, network – for lab/fab integration. | | Programming Reference (C/STIL/Pattern) | Pattern formats, timing sets, levels, vector memory mapping. | This means every pin is independent, allowing for
If you are looking for specific , or need help with load board schematic requirements , please let me know. To help you find the exact information you need, tell me: The SmarTest version you're using (e.g., 7.x, 8.x)